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Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS
Re: Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS
i should stick with F5 and try to find the timings/settings for the 2x2GB kit, or flash to the latest F6 ?
I would flash to the latest bios using the QFLASH utility your board came with. Be sure to set your bios to Load optimized defaults first though. Here is a great tutorial for Flashing a bios on all the latest Gigabyte boards. http://forums.tweaktown.com/f69/bios...h-guide-27576/
the stock bios wont detect the 955BE correctly.
then i flash the bios to the latest F5, problem solved, now windows 7 ultimate 64 can detect the 955BE correctly.
i notice the description said :
F6 (2009/09/16) Update CPU ID (Support AGESA 3.5.3.1 code / AM3 C3 CPU)
F5 (2009/08/06) Update CPU ID(AGESA 3.5.3.0 for PhenomII /AthlonII AM3 CPU)
Warning:
Because BIOS flashing is potentially risky, if you do not encounter problems using the current version of BIOS, it is recommended that you not flash the BIOS. To flash the BIOS, do it with caution. Inadequate BIOS flashing may result in system malfunction.
so... does that mean, i should stick with F5 and try to find the timings/settings for the 2x2GB kit, or flash to the latest F6 ?
Re: Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS
hi all, i got a problem setting the patriot 2x2gb ddr3 llk kit, it's not working in dual channel mode on my ma790xt-ud4p. i already post the details here :
Re: Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS
Well tRAS is a "Usually" type of thing, sometimes it can differ. You can see the same noted here by the maker of Memset Tweakers.fr
tRD, ya it can be mysterious at times, it's new tech so ya never know what to expect.
From the above linked site
-Performance Level / Read Delay (tRD).
tRD is the number of memory clocks from DRAM Chip Select# assert
to Host Data Ready# assertion on the FSB.
Hight influence on performance and stability.
Re: Memory Timings Explained W/ Suggested Timings & Memset VS. BIOS
Hi Lsdmeasap,
Thanks for all the wonderful info here: When I recently bought a new PC, it helped me immensely in understanding all about the RAM technology I now had. I googled and researched a lot, and there are a couple of things that might be of interest (or at least my noobishness might entertain!)
1) You write:
tRAS = tCL + tRCD + tRP (+/- 1) so that it gives everything enough time before closing the bank.
... Everybody else says that also, but I don't think that's right!
Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
... a diagram in that PDF shows "RAS Cycle Time = Bank Active time + Bank Precharge time": i.e. Bank Active is followed by Precharge.
(It also shows: "RAS Cycle Time >= tRC, Bank Active >= tRAS, Bank Precharge time >= tRP".)
If Bank Active time preceeds and does not include Precharge, how can tRAS = tCL + tRCD + tRP (+/- 1)?
I suspect actually that, tRAS = tCL + tRCD + tXXX, where tXXX is some unspecified internal chip operation minimum time, and that tXXX just happens to be have the same numerical value as tRP (+/- 1), in the same way that tCL, tRCD & tRP just happen to often have the same numerical value.
2) Isn't tRD a little mysterious?
I googled high and wide and even download a few Intel MCH spec docs, and tRD is not documented for recent DDR2 MCH chips!
It is surely an MCH configuration value, but not documented. I did find a forum post by the author of the memset program where he and others were discussing which MCH register it was in.
As near as I can tell, tRD is more or less the equivalent to tCL, but on the CPU/MCH side of the bus, rather than on the MCH/Memory side of the bus.
(tCL is the clock delay - memory clock - between the MCH giving a read command (CAS) to the memory and data becoming available, whereas tRD is the clock delay - CPU FSB clock - between the CPU giving a read command to the MCH and data becoming available.)
Given that tCL is just about the most important memory parameter, and the one of the first things that people tweak, it's surprising that many 'how to tweak memory speed' articles don't even mention tRD.
The AnandTech: ASUS ROG Rampage Formula: Why we were wrong about the Intel X48 link on the first page of this thread is about the only place I found that talked about it in depth. They have a formula which can more-or-less be arranged into:
tRD > (tCL + x) * FSB / DRAM_Freq
...where 'x' is a funny parameter not explained well.
I'd like to think x is tCCD (usually =2?), because that would make sense given the process. Or perhaps the formula is:
tRD > (tCL / DRAM_Freq + x) * FSB
... where x = 5/1000 (5ns, plucked out of the air...)
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